John J. Lee, Ph.D. Associate Professor Department of Electrical and Computer Engineering Purdue School of Engineering and Technology Indiana University-Purdue University Indianapolis 723 West Michigan St. SL 160, Indianapolis, IN 46202-5132 Tel: 317-278-2267, Fax: 317-274-4493, Email: johnlee at iupui.edu

Research with Me

• General Policy
• Writing Technical Paper or Article with Me
• Effective Oral Presentation and Its Preparatioin
• Toward a Successful PhD Student
• How To Write Thesis

Research Interests (listed recent to past)

• Topics
• Bitcoin Blockchain Technology
• Ethereum Smart Contract Blockchain Technology
• HyperLedger Blockchain Technology

• The Internet of Things (IoT) is the network of physical objects or "things" embedded with electronics, software, sensors, and network connectivity, which enables these objects to collect and exchange data with Internet. In other words, IoT is the intelligent connectivity of physical devices, driving massive gains in efficiency, business growth, and quality of life.
• Topics
• Building Private LoRaWAN Platforms and Application Developments
• Developing an IoT-based water quality and infrastructure monitoring system
• Development of Big Data technology for improved restroom safety and basic health utilizing IoT
• 2016 AgBot Challenge
• 2017 AgBot Challenge
• 2018 AgBot Challenge
• 2019 AgBot Challenge
• IoT Tools and Components
• Software
• OpenHAB, Node-RED, Java, JavaScript, Python, MySQL, MongoDB, IFTTT, Temboo, MQTT, etc.
• Hardware
• LoRaWAN, Raspberry Pi, Arduino, ESP8266, ZigBee, nRF24, etc.

• Massive parallel computation on your PC now possible with GPUs
• Topics
• InPore for CFD modeling of porescale porous media flows
• Parallel Processing of Fast 3D Image Registration Using GPU for Clearer AOOCT Volume Images
• GPU-accelerated Real-time MHz-rate Multi-camera AO-OCT Image Processing
• Matrix-based XML/JSON Stream Processing using GPU
• GPU-accelerated Data Stream Processing
• A GPU-oriented Online Recommendation Algorithm for Efficient Processing of Time-varying Continuous Data Streams
• GPU-accelerated Outlier Detection for Continuous Data Streams
• RDF and HDT Triple Search Acceleration using GPU
• Bit-Vector GPU-based Deadlock Detection Algorithm for Single-Unit Resource Systems and Multi-Unit Resource Systems
• Electronic Health/Medical Record Data-mining Acceleration Using GPU
• Parallel Particle Swarm Optimization Using GPU
• Statistical Analysis Of Large Data Sets Using GPU

• Reconfigurable Logic (RL) coprocessors such as FPGAs are commodity hardware accelerators that show significant promise in accelerating computation. However, these coprocessors have not been explored comprehensively within database research. Our group's long-term vision is to provide a comprehensive and demonstrative approach to integrate and use RL coprocessors as database accelerators in fast, extensible reconfigurable logic assisted database management systems.

• Our hardware implementation of a software algorithm is a fully hardware oriented implementation exploiting maximum hardware parallelism of all computations of the original algorithm. This methodology reduces not only algorithm execution time but also the run-time complexity.
• Past designs: O(1) Deadlock Detection Hardware, O(min(m,n)) Deadlock Detection Hardware, Deadlock detection and avoidance hardware, Parallel Banker's Algorithm in hardware

• Constructing a quality simulator requires tremendous efforts. Moreover, modifying an already built simulator to use to explore various characteristics of the components of the simulator is also non-trivial task and typically time-consuming and error-prone. To overcome this drawback, researchers have invented Architecture Description Language (ADL) that can be used to specify instruction set architecture. ADL is typically designed to have simple syntax and thus easier to understand, which enables not only to easily build a computer simulator and its tool suite but also to easily modify and explore design space of the modelled system. Furthermore, ADL enables users to automatically generate different simulators with different parameters and components.

• Lack of educational computer architecture simulators in the academia hinders learning process of EE, ECE and CS students in computer architecture. Overcoming such impediment requires good modularized visually enhanced computer architecture simulators that demonstrate how critical components of processors operate. Such components are MIPS pipeline, scoreboarding, tomasulo and superscalar structures, shown in popular computer organization books. To help students grasp such topics easier, we develop an educational instruction set simulator with visualization using a recent new programming language C#.

• Implementing a full system simulator for hybrid systems with multicore processors and FPGAs.

Current Students

• Valli Sanghami Shankar Kumar, PhD student
• Linknath Surya Balasubramanian, PhD student

Past Students

• Tareq Alqaisi (IUPUI MSECE, Dec. 2017), Current Employment: Endress+Hauser Inc.
• Thesis: Microblaze-based Coprocessor for Data Stream Management Systems
• Chandima Hewanadungodage (Purdue Univ. PhD. Dec. 2016), Current Employment: Rosen Center for Advanced Computing (RCAC)
• PhD Dissertation: Accelerating Data Stream Mining Applications using Graphics Processing Units
• Nhan Do (IUPUI MSECE, July 2016), Current Employment: Google
• Thesis: Parallel Processing for Adaptive Optics Optical Coherence Tomography (AO-OCT) Image Registration using GPU
• Pranav S. Vaidya (Purdue Univ. PhD. Dec. 2015 and IUPUI MSECE, Aug. 2007), Current Employment: NVIDIA
• MS Thesis: Towards Parallel Multithreaded Simulation of Multicore Processors and Reconfigurable Logic Coprocessors
• PhD Dissertation: Hardware-Software Co-designed Data Stream Management Systems
• Jeffery Kriske Jr. (IUPUI MSCS, Dec. 2014), Current Employment: Eli Lilly and Company
• Thesis: A Scalable Approach to Processing Adaptive Optics Optical Coherence Tomography (AOOCT) Data from Multiple Sensors Using Multiple Graphics Processing Units (GPUs)
• Joe Perrin (IUPUI MSECE, Dec. 2014), Current Employment: Technicolor
• Research: Statistical analysis of large data sets using GPGPU computing: Relationship between Brain scan (MRI) volume and DNA in the Alzheimer's disease
• Brandon Shafer (IUPUI MSECE, May 2014), Current Employment: Phoenix Data Corporation
• Thesis: Real-time Adaptive-optics Optical Coherence Tomography (AOOCT) Image Reconstruction on a GPU
• Stephen Abell (IUPUI MSECE, June 2013), Current Employment: Boeing
• Thesis: Parallel Acceleration of Deadlock Detection and Avoidance Algorithms on GPUs
• James Schmidt (IUPUI MSECE, Aug. 2011), Current Employment: Intel at Portland, Oregon
• Thesis: Towards Many-Core Processor Simulation On Cloud Computing Platforms
• Christopher Barnes (IUPUI MSECE, Aug. 2010), Current Employment: L3 Communications in Utah
• Thesis: A Dynamically Configurable Discrete Event Simulation Framework for Many-Core System-on-Chips
• Jonathon Brack (IUPUI MS, May 2010), Current Employment: Technicolor
• Xiang Xiao (Purdue Univ. PhD. Aug. 2009), Current Employment: Google
• Dissertation: Hardware-oriented Parallel Deadlock Detection Algorithms with Reduced Run-time Complexity

Education

• Ph.D., Electrical and Computer Engineering, Georgia Tech, Atlanta, GA, 2004
• Dissertation: Hardware/Software Deadlock Avoidance for Multiprocessor Multiresource System-on-a-Chip
• M.S., Electrical and Computer Engineering, Georgia Tech, Atlanta, GA, 2003
• B.S., School of Electrical Engineering and Computer Science, Kyungpook National University, Korea

Professional

• Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, Adjuct Professor, 2014-2017
• Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, Visiting Professor, 2012
• Agency for Defense Development (ADD), Korea, Researcher, 1986-2000